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1. Energy-efficiency limits of digital circuits based on CMOS transistors Elad Alon; 2. Beyond transistor scaling: alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 3. Benchmarking alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 4. Extending CMOS with negative capacitance Asif Islam Khan and Sayeef Salahuddin; 5. Designing a low voltage, high current tunneling transistor Sapan Agarwal and Eli Yablonovitch; 6. Tunnel transistors Alan Seabaugh, Zhengping Jiang and Gerhard Klimeck; 7. Graphene and 2D crystal tunnel transistors Qin Zhang, Pei Zhao, Nan Ma, Grace (Huili) Xing and Debdeep Jena; 8. Bilayer pseudospin field effect transistor Sanjay Bannerjee, Frank Register and Dharmendar Reddy; 9. Computation and learning with metal-insulator transitions and emergent phases in correlated oxides You Zhou, Sieu D. Ha and Shriram Ramanathan; 10. The piezo-electronic transistor Paul M. Solomon, Bruce G. Elmegreen, Matt Copel, Marcelo A. Kuroda, Susan Trolier-McKinstry, Glenn J. Martyna and Dennis M. Newns; 11. Mechanical switches Tsu-Jae King Liu and Rhesa Nathanael; 12. Nanomagnetic logic: from magnetic ordering to magnetic computing Gy鰎gy Csaba, Gary H. Bernstein, Alexei Orlov, Michael T. Niemier, X. Sharon Hu and Wolfgang Porod; 13. Spin torque majority gate logic Dmitri E. Nikonov and George I. Bourianoff; 14. Spin wave phase logic Alexander Khitun; 15. Interconnect considerations Ahmet Ceyhan, Shaloo Rakheja and Azad Naeemi.

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