Preface; 1. THE BASICS; 1.1: Simple NMOS Logic Gates; 1.2: Simple CMOS Logic Gates; 1.3: Computer Simulation; 1.4: Transfer Curves and Noise Margins; 1.5: Gate Delays and Rise and Fall Times; 1.6: Transient Response; 1.7: An RC Approximation to the Transient Response of a CMOS Inverter; 1.8: Summary; 1.9: Bibliography; 1.10: Problems; 2. PROCESSING, LAYOUT, AND RELATED ISSUES; 2.1: CMOS Processing; 2.2: Bipolar Processing; 2.3: CMOS Layout and Design Rules; 2.4: Advanced CMOS Processing; 2.5: Bibliography; 2.6: Problems; 3. INTEGRATED-CIRCUIT DEVICES AND MODELING; 3.1: Simplified Transistor Modeling; 3.2: Semiconductors and pn Junctions; 3.3: MOS Transistors; 3.4: Advanced MOS Modeling; 3.5: Bipolar-Junction Transistors; 3.6: SPICE-Modeling Parameters; 3.7: Appendix; 3.8: SPICE Simulations; 4. TRADITIONAL MOS DESIGN; 4.1: Pseudo-NMOS Logic; 4.2: Pseudo-NMOS Logic Gates; 4.3: Transistor Equivalency; 4.4: CMOS Logic; 4.5: CMOS Gate Design; 4.6: SPICE Simulations; 4.7: Bibliography; 4.8: Problems; 5. TRANSMISSION-GATE AND FULLY DIFFERENTIAL CMOS LOGIC; 5.1: Transmission-Gate Logic Design; 5.2: Differential CMOS Circuits; 5.3: Bibliography; 5.4: Problems; 6. CMOS TIMING AND I/O CONSIDERATIONS; 6.1: Delay of MOS Circuits; 6.2: Input/Output Circuits; 6.3: Bibliography; 6.4: Problems; 7. LATCHES, FLIP-FLOPS, AND SYNCHRONOUS SYSTEM DESIGN; 7.1: CMOS Clocked Latches; 7.2: Flip-flops; 7.3: CMOS Flip-flops; 7.4: Synchronous System Design Techniques; 7.5: Synchronous System Examples; 7.6: Bibliography; 7.7: Problems; 8. BIPOLAR AND BiCMOS LOGIC GATES; 8.1: Emitted-Coupled Logic Gates; 8.2: Current-Mode Logic; 8.3: BiCMOS; 8.4: SPICE Simulations; 8.5: Bibliography; 8.6: Problems; 9. ADVANCED CMOS LOGIC DESIGN; 9.1: Pseudo-NMOS and Dynamic Precharging; 9.2: Domino-CMOS Logic; 9.3: No-Race-Logic; 9.4: Single-Phase Dynamic Logic; 9.5: Differential CMOS; 9.6: Dynamic Differential Logic; 9.7: Bibliography; 9.8: Problems; 10. DIGITAL INTEGRATED SYSTEM BUILDING BLOCKS; 10.1: Multiplexors and Decoders; 10.2: Barrel Shifters; 10.3: Counters; 10.4: Digital Adders; 10.5: Digital Multipliers; 10.6: Programmable Logic Arrays; 10.7: Bibliography; 10.8: Problems; 11. INTEGRATED MEMORIES; 11.1: Static Random-Access Memories; 11.2: Static Random-Access Memory Storage Cells; 11.3: Address Buffers and Decoders; 11.4: Dynamic Bus Precharge and Address-Transition-Detect Circuits; 11.5: Modifications for Large Static Random-Access Memories; 11.6: Dynamic Random-Access Memories; 11.7: Read-Only Memories; 11.8: Bibliography; 11.9: Problems; 12. GaAs DIGITAL CIRCUITS; 12.1: Introduction; 12.2: GaAs Processing and Components; 12.3: MESFET Modeling; 12.4: MESFET Second-Order Effects; 12.5: Logic Design with MESFETs; 12.6: Capacitively Enhanced Logic; 12.7: GaAs Logic Family Comparison; 12.8: Heterojunction Bipolar Technology; 12.9: Bibliography; 12.10: Problems; 13. DIGITAL SYSTEM TESTING; 13.1: Conservative Design Principles; 13.2: Scan-Design Techniques; 13.3: Localized Test-Vector Generation and Test-Output Compression Techniques; 13.4: Boundary-Scan Testing; 13.5: Bibliography; 13.6: Problems
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